Use of NAND Flash Based Devices in Aerospace Applications
This post describes the design requirements for NAND FLASH devices (SSD) used in Aerospace applications. These applications cover commercial satellites that may be used for weather data collection, telecommunications, or full spaceship deployment.
When one thinks of Aerospace, NASA naturally comes to mind. NASA has strict requirements for any device to be deployed in outer space aircraft. These requirements far exceed even the strictest military specifications, which are very strict, to begin with. So any product put forth must meet the military specifications and then some — no small task.
General Goals for Aerospace SSD Product
Many storage devices for space applications have architectures that limit data transfer speeds. These architectures also fail to include error correction algorithms to counter the effects of ionizing radiation damage to the flash memory storage elements. In a previous paper, we discussed the effects of radiation on NAND Flash based devices. In particular susceptibility to single-event effects (SEE) and total ionizing dose (TID) degradation, most NAND devices are subject to corrupted data naturally arising during normal operating conditions. Because of this, NAND devices utilize tools such as error correction code (ECC) algorithms that can detect and correct errors that occur during the read process, ensuring data is being read correctly, as well as protecting data from corruption.
Space-grade SSDs generally require Flash controllers with sophisticated ECC, paired with large geometry industrial-grade single-level cell (SLC) NAND flash memory. Our previous paper suggested such ECC algorithms as well as designing for fault tolerance and long-term data integrity.
Applications vary, but in general, there are basic testing requirements for Aerospace deployed devices, generally conducted by Independent certified laboratories, in the following areas:
Temperature, Humidity, Salt Spray, UV Light, Fluid Susceptibility,
Altitude/over-pressure/decompression, waterproofing, Icing, teardown, Thermal Vacuum, fungus, Sand and dust
Shock and Vibration, Static Load, Acceleration, Bending Susceptibility, Pull Force
EMI, EMC, ESD, HIRF, Lightning
Total Dose (TID), Proton, Heavy Ionizing-dose, Californium-CF-252
Acoustic Noise, Transmission loss
Qualifying by passing these tests is no easy task. Special design techniques for the complete device, including packaging design must be adhered to. For example, PC board assemblies must be conformal coated. All components must be specially selected for temperature extremes, humidity, and heat tolerance etc.
Devices will need to be properly sealed to meet many of these requirements. This then brings up other issues such as temperature rise inside the enclosure. A 15°C rise above ambient is not uncommon, dependent internal power consumption and heat dissipation.
So very careful attention must be paid to both power consumption and thermal management. Luckily, the use of CMOS helps here.
For ESD, clamping devices such as Transorbs are used, along with careful PCB layout and enclosure design.
For EMI/EMC, spread spectrum oscillators are often used. This along with careful RF gaskets and enclosure design help to meet both radiated emissions and radiation susceptibility.
There is no room for error or failure in these SSD devices. What does that mean? It means there must be robust ECC at the controller level for correcting NAND read errors. Robust wear leveling is a requirement. Recovery from potential errors from temporary power outages and unwanted stimulus.
In a previous paper, we mentioned TMR or Triple mode redundancy for NAND Flash devices. This is a low-level solution using a 24-bit data bus. There are more stringent redundancy measures that may have to be taken, both at a component level and possibly even at the device level.
At the component level, redundant Flash devices and even controllers can be used. Some designs may have to tolerate the failure of multiple NAND devices and controllers. Doing this can reduce read/write speeds, so there is, as always a tradeoff.
A more expensive route is to use a RAID configuration, which is an array of multiple SSD drives, whereby if one or more fail, the remaining drives can maintain data. There are different modes of RAID used in Enterprise servers today. It is actually quite common and very effective. Again the cost is a tradeoff. In extreme applications, component level redundancy and device level redundancy can be used.
Robust power cycling testing must result in no data lost. This is dependent on the controller firmware, as well as the surrounding hardware support. This isn’t simple to implement, and only the best controllers handle this properly.
SSD life is extremely important, and this requires a very effective wear leveling scheme for the NAND flash devices. The best wear leveling uses a static implementation. This scheme makes optimum use of the Flash, since all flash bocks are cycled, even if little to no data is written to them, for example, the FAT area of an SSD.. Not cycling this area can lead to read disturbances, resulting in drive corruption.
Shock and vibration are usually hard to meet with rotating drives, but easier to meet with SSD’s. However, careful attention must still be paid to packaging design. The levels of shock and vibration applied to Aerospace product far exceeds what is applied to commercial or Industrial products. So isolation of internals to attenuate these stimuli must still be addressed.
SSD devices are subject to data corruption even under terrestrial conditions. In Aerospace applications, disturbances are greatly magnified, requiring a totally different design approach. Design for error and failure-free operation, under the harshest of environments, must be undertaken. This is difficult enough for most products, but even more difficult for SSD devices due to the storage media deployed. No room for failure or error is the key to a successful SSD design for the Aerospace industry.
If one intends to enter this segment of the SSD market, study the specifications, be well prepared and no surprises will ensue.
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Carmine C. Cupani, MSEE
CTech Electronics LLC