Understanding NAND Flash-Based SSD Drives and the Flash Controller

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When you’re selecting industrial embedded storage for your application, having a thorough understanding of how different drives work makes it easier to pick the best fit for your needs. For most industrial device designers and engineers, flash-based SSD, or solid state drives, are reliable storage that works predictably in rugged operating conditions. What exactly makes SSD flash drives so desirable for industrial operations, and how does the flash actually work? Here is a closer look at NAND flash-based SSD drives and flash controllers.

A Primer on SSDs

Solid state drives, or SSDs, have increasingly replaced mechanical, hard disk drives (HDDs) in everything from personal computers to complex industrial applications. For industrial users, SSDs have the benefit of reliability and tolerance of extreme conditions. HDDs, as mechanical storage systems, have a spinning disk on which data is stored. In order to write or read data, the disk has to fire up and spin. In industrial operating conditions, however, it’s common for high levels of shock and vibration to be present. This kind of jostling of the device can cause the mechanical system in an HDD to become disjointed or misaligned, putting critical data at risk. The spinning system also requires time to begin to work, thus slowing down the operation of the device.

SSDs eliminate the risk of this kind of malfunctioning because they do not contain any moving parts. They are also faster than HDDs and better able to tolerate extreme temperatures that are common in industrial operating conditions. That doesn’t mean that SSDs are without challenges, however, particularly for engineers attempting to get flash controllers to match the corrected bit error rate of HDDs. The hardware architecture of NAND flash is where these issues originate, especially within certain designs of SSDs and flash memory. This hardware is made up of:

Minimum four layers of PCB
NAND flash controller
NAND flash devices (SLC, MLC, TLC, or pSLC)
Exterior enclosure, based on the form factor
Power supply

Despite the sophistication of the hardware, the most critical component of the success of a NAND-flash SSD is the NAND flash controller, which relies upon sophisticated hardware and firmware for seamless operations.

NAND Flash Controller Hardware

NAND flash controller hardware is made up of multiple parts:

Host Interface: This part communicates in both directions between the drive and the host device, using the relevant protocol. It uses flash access and Direct Memory to offload to the firmware. Common interfaces are PATA, SATA, SD, USB, and MMC.
Flash Bus Interfaces: The bus can interface with one or multiple flash devices, regardless of whether it is SLC, MLC, TLC, or pSLC. In some cases, there may be a combination of flash formats. The bus typically has multiple channels with interleaving within the channels, increasing input by creating parallelism for data transfers.
Direct Memory and Flash Access: Also known as DMA and DFA, these buffers increase throughput by allowing transfers to and from RAM and flash without intervention from the CPU.
Error Detection and Correction: This is a critical component of the hardware, since it allows data errors to be caught in real time. Small-process MLC and TLC flash rely on this component the most. It is necessary to have 96 bits of correction, or more.
Data Scrambler: Modern MLC and TLC flash memory use a data scrambler. This allows encryption to happen faster, especially when combined with DMA and DFA. Some older NAND flash designs rely on the encryption unit alone to complete these tasks.
Data Encryption: Data encryption and decryption is achieved by generated security keys to access all data, even the firmware. For industrial applications, this is a critical component that can only be achieved as part of the hardware design.
SRAM: Firmware, sector buffers, temporary files, and more reside in SRAM. Parity with SRAM is becoming a crucial part of NAND flash hardware.

An optional component of NAND flash hardware is ISO 7816 Secure Serial Data Port. For SD and SDIO cards, this component is required.

NAND Flash Controller Firmware Structure

Each NAND flash controller has a ROM built in that works similarly to a BIOS in a PC. The ROM code is responsible for CPU initialization, basic flash initialization and resets, and putting the host on a busy status. It will look for flash devices that have been initialized, search for a key that shows that firmware has been installed, and will then install the basic structure that is required. The ROM should load the firmware part that lives in the first flash device.

The power-up procedure triggered by the ROM happens quickly. After loading the resident firmware, the firmware scans the flash drive for any errors and makes the corrections needed. It then releases the busy at the host port so that the drive can receive commands. If the process is extended for any reason, it increases the risk of issues occurring between the drive and the host device.

The firmware is written in modular form. A typical exam is as follows:

Power-up process
Host interface process
Flash transition layer
Flash read/write procedures (this is usually aided by the DMA and DFA hardware)
Encryption and decryption (also aided by the hardware)
Customer-specific add-on hooks
Debugging process

Spotlight on Flash Transition Layer

The Flash Transition Layer, or FLT, is the most critical part of the firmware when it comes to performance of the flash. It carries the brunt of the work done by the firmware and includes the following components:

Logical to Physical Mapping Processes: In SSDs, the unit of transfer of data is known as a sector or Logical Block Address (LBA). These units must be stored physically. This means that storage is in the NAND flash, for SLC, MCL, TLC, and pSLC. These blocks of data typically consist of multiple pages.
Logical to Physical Mapping Tables: These tables provide the location of all the LBAs that are in the physical blocks in the flash. Block-based and physical-based mapping are the most common schemes used. Tables are generally very large, since they represent large amounts of data.
Defective Flash Block Tables: Most flash vendors guarantee customers that no more than 2% of data blocks will be defective, but some issues are inevitable. Defective flash block tables may contain only the data blocks that were defective when the flash came from the manufacturer, while others contain manufacturer defects as well as dynamic defects that happen while the flash is in use. In other cases, dynamic defects are simply removed as they occur.
Flash Log Blocks: These blocks store a record of the most recent transactions of the flash and are part of the tables. The blocks are loaded in RAM and then sent to flash completion of the transaction being recorded.
Spare Flash Block Tables: When dynamic defects happen, these spare flash blocks replace the defective blocks. The tables have the physical addresses of all of the blocks. It’s important to have an adequate number of spare blocks available in the flash to prevent data loss in the case of a malfunction.
Wear Leveling: Wear leveling is key to ensuring that SSDs last for as long as possible. NAND flash memory has a limited lifespan that is determined by the number of program and erase (P/E) cycles the blocks can withstand. Wear leveling ensures that the blocks are used evenly, preventing the flash from wearing out too soon because of excessive use of a small number of blocks.

More Important NAND Flash SSD Features

For error detection and correction, the hardware and firmware work in conjunction with each other. Error detection happens in the hardware, which triggers a response by the firmware, which deals with the administration of errors. Generally, the hardware has a counter to keep track of the number of errors that occur and will trigger a refresh of a block that is seeing high levels of error corrections.

Read disturb management is another feature that allows the hardware and firmware to increase the efficiency of the flash. Because NAND flash blocks only allow a certain number of read cycles before a P/E cycle occurs, read disturb management keeps track of the read counts for blocks and moves data to a block with fewer reads when the count reaches a number that is close to triggering a P/E cycle. For SLC flash, which is most commonly used by industrial applications, this number is usually around one million reads.

Learn More About Industrial Embedded Memory from Delkin

Choosing industrial flash memory for your application depends on a number of factors, from the design of your device to its operational environment. Delkin is here to help you get the best fit for you needs and to answer all of your questions about how NAND flash-based SSDs work. Contact us today to learn more.

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